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philips semiconductors pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom product data supersedes data of 2002 may 24 2003 jun 27 integrated circuits
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2 2003 jun 27 features ? 5-bit 2-to-1 multiplexer, 1-bit latch dip switch ? 6-bit mux_outx and non_muxed_out eeprom programmable and readable via i 2 c-bus ? 5 v tolerant open drain mux_outx and non_muxed_out outputs ? active-low override input forces all mux_outx outputs to logic 0 ? i 2 c readable mux_inx inputs ? 5 v tolerant open drain i/ox pins, power-up default as outputs ? 1 address pin, allowing up to 2 devices on the i 2 c-bus ? active-low reset input with internal pull-up for the 8 i/o pins ? 2048-bit eeprom programmable and readable via the i 2 c or i/os ? operating power supply voltage range of 3.0 v to 3.6 v ? smbus compliance with fixed 3.3 v levels ? 2.5 v to 5 v tolerant inputs ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jesdec standard jesd78 which exceeds 100 ma description the pca9558 is a highly integrated, multi-function device that is composed of a 5-bit multiplexed/1-bit latched 6-bit i 2 c/smbus eeprom dip switch, an 8-bit i/o expander and a 2-kbit serial eeprom with write protect. the pca9558 integrates these commonly used components into a single chip to reduce component count and board space requirements and is useful in computer, server and telecom/networking applications. multiplexed/latched eeprom dip switch ? used to select digital information between a set of 5-bits of default hardware inputs and an alternative set of inputs provided by the i 2 c/smbus interface and stored in the eeprom. examples of this type of selection include processor voltage configuration or processor vendor identification (vid). the multiplexed/latched eeprom can also be used to replace dip switches or jumpers, since the settings can be easily changed via i 2 c/smbus without having to power down the equipment to open the cabinet. the non-volatile memory retains the most current setting selected before the power is turned off. 8-bit i/o expander ? used to control, monitor or collect remote information or power leds. monitored or collected information can be read through the i 2 c/smbus or can be stored in the internal eeprom. 2-kbit serial eeprom ? used to store information such as card identification or revision/maintenance history on every motherboard/linecard and can be read or written via i 2 c/smbus when required. the pca9558 has 1 address pin allowing up to 2 devices to be placed on the same i 2 c-bus or smbus. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 28 scl sda i/o_out_low a0 mux_ina mux_inb mux_inc mux_ind mux_ine gnd i/o0 v dd wp mux_out_low non_muxed_out mux_outa mux_outb mux_outc mux_oute mux_outd mux_select i/o7 i/o6 i/o1 13 16 i/o5 i/o2 14 15 i/o4 i/o3 sw00614 figure 1. pin configuration ordering information packages temperature range order code topside mark drawing number 28-pin plastic tssop 0 to +70 c PCA9558PW pca9558dh sot361-1 standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 3 pin description pin number symbol function 1 scl serial i 2 c-bus clock 2 sda serial bi-directional i 2 c-bus data 3 i/o_out_low active-low control forces all gpio to logic 0 outputs 4 a0 a0 address 5-9 mux_in a-e external inputs to multiplexer 10 gnd ground 11-18 i/o[0-7] general purpose input/output 0 through 7 (open drain outputs) 19 mux_select active-low select of mux_in inputs or eeprom contents for mux_out outputs 20-24 mux_out e-a open drain multiplexed outputs 25 non_muxed_out open drain outputs from non-volatile memory 26 mux_out_low active-low control forces all mux outputs to logic 0 27 wp active-high eeprom write protect 28 v dd power supply : +3.0 to +3.6 v
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 4 block diagram 5 i 2 c interface logic mux_in 256 byte eeprom gpio i 2 c control logic latch 8 5 mux select mux_out_low non_muxed_out i/o0-7 mux_oute mux_outd mux_outc mux_outb mux_outa sw00633 write protect 1 0 i/o_out_low a0 pca9558 sda scl v dd gnd power-on reset 5-bit 2 to 1 multiplexer 6-bit eeprom input filter nmo figure 2. block diagram
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 5 i 2 c interface communicating with this device is initiated by sending a valid address on the i 2 c-bus. the address format (see figure 3) has 6 fixed bits and one user-programmable bits followed by a 1-bit read/write value which determines the direction of the data transfer. 10 0 1 1a0 fixed hardware selectable r/w 1 lsb msb figure 3. i 2 c address byte following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the eeprom. data will be written to the register if the read/write bit is logic 0 and the wp input is logic 0. data will be read from the register if the bit is logic 1. the four high-order bits are latched outputs, while the four low order bits are multiplexed outputs (figure 5). note: 1. to ensure data integrity, the eeprom must be internally write protected when v cc to the i 2 c-bus is powered down or v cc to the component is dropped below normal operating levels. d7 d6 d5 d4 d3 d2 d1 d0 figure 4. command byte lsb msb mux data a mux data b mux data c mux data d non- muxed data 0 0 mux data e figure 5. i 2 c mux_out data byte lsb msb mux_in e 0 0 mux_in d mux_in c mux_in b mux_in a 0 figure 6. i 2 c mux_in data byte table 1. command byte d7 d6 d5 d4 d3 d2 d1 d0 command 0 0 0 0 0 0 0 1 write to 256ee via i 2 c 0 0 0 0 0 0 1 1 read from 256ee via i 2 c 0 0 0 0 0 1 0 0 write to 6 bit ee via i 2 c 0 0 0 0 0 1 1 0 read from 6 bit ee via i 2 c 0 0 0 0 0 1 1 1 read ip (input port) register via i 2 c 0 0 0 0 1 0 0 0 read/write op (outut port) register via i 2 c 0 0 0 0 1 0 0 1 read/write pi (polarity inversion) register via i 2 c 0 0 0 0 1 0 1 0 read/write ioc (input/ouput configuration) register via i 2 c 0 0 0 0 1 0 1 1 read/write muxcntrl (mux control) register via i 2 c 0 0 0 0 1 1 0 0 read muxin values via i 2 c 0 0 0 0 1 1 0 1 reserved 0 0 0 0 1 1 1 0 reserved 0 0 0 0 1 1 1 1 read 256ee and write op register 0 0 0 1 0 0 0 0 read 256ee and write pi register 0 0 0 1 0 0 0 1 read 256ee and write ioc register 0 0 0 1 0 0 1 0 read ip register and write to 256ee 0 0 0 1 0 0 1 1 reserved 1 1 1 1 1 1 1 1 reserved
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 6 the multiplexer function controls the six open drain outputs, mux_outx and non_muxed_out. this control is effected by the input pins mux_select (pin 19), mux_out_low (pin 26), and/or an internal register programmed via the i 2 c-bus. upon power-up the multiplex function is controlled by the mux_select and mux_out_low pins. when the mux_select signal is a logic 0, the multiplexer will select the data from the 6-bit eeprom to drive on the mux_outx and non_muxed_out pins. when the mux_select signal is a logic 1, the multiplexer will select the mux_inx pins to drive on the mux_outx pins. the non_muxed_out output is latched from the 6-bit eepr om on a rising edge of the mux_select signal. this latch is transparent while the mux_select signal is a logic 0. an internal control register, written via the i 2 c-bus, can also control the multiplexer function. when this register is written, the mux_select function can change from the external pin to an internal register. in this register a bit will act in a similar fashion to the mux_select input, i.e., a log ic 1 will cause the multiplexer to select data from the 6-bit eeprom to drive on the mux_outx and non_muxed_out pins. in this configuration, the non_muxed_out will latch data when the pca9558 acknowledges the i 2 c-bus. the mux_select pin will have no effect on the mux_outx or non_muxed_out while in this mode. when the mux_out_low signal is a logic 0 and the multiplexer is configured so that the mux_outx pins are being driven by the 6-bit eeprom, the mux_outx pins will be driven to a logic 0. this information is summ arized in table 2. table 2. multiplexer function table reg. input output b1 3 b0 3 mux_out_low mux_select mux_outx non_muxed_out x 0 0 1 mux_inx inputs latched from eeprom 1 x 0 0 0 0 0 x 0 1 1 mux_inx inputs latched from eeprom 1 x 0 1 0 from eeprom from eeprom 0 1 0 x mux_inx inputs latched from eeprom 2 1 1 0 x 0 0 0 1 1 x mux_inx inputs latched from eeprom 2 1 1 1 x from eeprom from eeprom notes: 1. non_muxed_out value will be the value present in the 6-bit eeprom at the time of the rising edge of the mux_select input. 2. non_muxed_out value will be the value present int he 6-bit eeprom at the time of the slave ack when bit 1 has changed from ?0 ? to ?1?. 3. these are the 2 lsbs of the muxcntrl (mux control) register if the mux_outx outputs are being driven by the 6-bit eeprom and this eeprom is programmed, the outputs will remain stable and change to the new values after the eeprom program cycle completes. examples of read/write for mux control can be found in figure 7. s100111a0 0 a00001011 a p slave address r/w acknowledge from slave acknowledge from slave command byte data byte sw00635 000000b1b0 a acknowledge from slave figure 7. i 2 c write for muxcntrl register sw00636 s100111a00 a00001011 a slave address r/w acknowledge from slave acknowledge from slave command byte slave address s acknowledge from slave a 100111a01 p 000000b1b0na data from slave no acknowledge from master r/w figure 8. i 2 c read for muxcntrl register
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 7 the gpios are controlled by a set of 4 internal registers: input port register (ipr); output port register (opr); polarity inve rsion register (pir); and the input/output configuration register (iocr). each register is read/write via the i 2 c-bus or 256 byte eeprom, with the exception of the ipr, which is read only, one at a time. the read/write takes place on the slave acknowledge. the control of which regist er is currently available to the i 2 c-bus is set by bits in the control register. see tables 3 through 6 for details. table 3. input port register (ipr) bit i7 i6 i5 i4 i3 i2 i1 i0 default 0 0 0 0 0 0 0 0 this register is an input-only port. it reflects the logic value present on the gpio pins regardless of whether they are configured as inputs or outputs (iocr). writes to this register have no effect. table 4. output port register (opr) bit o7 o6 o5 o4 o3 o2 o1 o0 default 0 0 0 0 0 0 0 0 this register is an output-only port. it reflects the outgoing logic levels of the gpio defined as outputs in the iocr. bit values in this register have no effect on gpio defined as inputs. in turn, reads from this register reflect the value stored in the flip-flop controlling the output, not the actual output value. table 5. polarity inversion register (pir) bit p7 p6 p5 p4 p3 p2 p1 p0 default 1 1 1 1 0 0 0 0 this register enables polarity inversion of gpio defined as inputs by the iocr. if a bit in this register is set to a logic 1, the corresponding gpio input port is inverted. if a bit in this register is set to a logic 0, the corresponding gpio input port is not inverted. table 6. i/o configuration register (iocr) bit c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 this register configures the direction of the gpio pins. if a bit is set to a logic 1, the corresponding port pin is enabled as an input with a high impedance output driver. if a bit is set to a logic 0, the corresponding port pin is enabled as an output. examples of read/write to these registers can be found in figures 9, 10, 15, and 16. the i/o_out_low input, when held low longer than the time t w , will reset the gpio registers to their default (power-up) values. a read of the present value of the inputs mux_inx can be done via the i 2 c. this is done by addressing the pca9558 in a write mode and entering the correct command code. the preset value on the mux_inx inputs is latched at the command code acknowledge. a repeated start is then sent with the r/w bit set to a logic 1, read, and this latched data is read out on the i 2 c-bus. see figure 11.
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 8 sw00637 s100111a0 0 a0000 slave address r/w acknowledge from slave acknowledge from slave command byte data byte acknowledge from slave xxxxa p d7 d6 d5 d4 d3 d2 d1 d0 a see figure 2 for the proper command byte figure 9. i 2 c write for gpio registers sw00638 s100111a00 a a slave address r/w acknowledge from slave acknowledge from slave command byte slave address s acknowledge from slave a 100111a01 p d7 d6 d5 d4 d3 d2 d1 d0 na data from slave no acknowledge from master r/w 0000xxxx figure 10. i 2 c read for gpio registers sw00639 s100111a00 a a slave address r/w acknowledge from slave acknowledge from slave command byte slave address s acknowledge from slave a 100111a01 p 0 0 0 d4 d3 d2 d1 d0 na data from slave no acknowledge from master r/w 00001100 figure 11. i 2 c read of mux_inx inputs
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 9 eeprom write operation 6-bit write operation a write operation to the 6-bit eeprom requires that an address byte be written after the command byte. this address points to the 6-bit address space in the eeprom array. upon receipt of this address, the pca9558 waits for the next byte that will be written to the eeprom. the master then ends the transaction with a stop condition on the i 2 c. see figure 12. after the stop condition, the e/w cycle starts, and the parts will not respond to any request to access the eeprom array until the cycle finishes, approximately 4 ms. 6-bit read operation a read operation is initiated in the same manner as a write operation, with the exception that after the word address has been written a repeated start condition is placed on the i 2 c-bus and the direction of communication is reversed (see figure 13). 256 byte write operation (i 2 c) a write operation to the 256 byte eeprom requires that an address byte be written after the command byte. this address points to the starting address in the eeprom array. the four lsbs of this address select a position on a 16 byte page register, the 4 msbs select which page register. the four lsbs will be auto-incremented after receipt of each byte of data; in this manner, the entire page register can be written starting at any point. up to 16 bytes of data may be sent to the pca9558, followed by a stop condition on the i 2 c-bus. if the master sends more than 16 bytes of data prior to generating a stop condition, data within the address page will be overwritten and unpredictable results may occur. see figure 14. after the stop condition, the e/w cycle starts, and the parts will not respond to any request to access the eeprom array until the cycle finishes, approximately 4 ms. 256 byte read operation (i 2 c) a read operation is initiated in the same manner as a write operation, with the exception that after the word address has been written, a repeated start condition is placed on the i 2 c-bus, and the direction of communication is reversed. for a read operation, the entire address is incremented after the transmission of each byte, meaning that the entire 256 byte eeprom array can be read at one time. see figure 15. 256 byte eeprom write to gpio a mode is available whereby a byte of data in the 256 byte eeprom array can be written to the gpio (opr). this is initiated by the i 2 c-bus. in this mode, a control word indicating a read from the 256 byte eeprom and write to the gpio is sent, followed by the word address of the data within the eeprom array. upon acknowledge from the slave, the data is sent to the gpio. see figure 16. 256 byte eeprom write from gpio a mode is available whereby data in the gpio (ipr) can be written to the 256 byte eeprom. this is initiated by the i 2 c-bus. in this mode, a control word indicating a read from the gpio and write to the 256 byte eeprom is sent, followed by the word address for the data to be written. once the slave sent an acknowledge, the master must send a stop condition. see figure 17. after the stop condition, the e/w cycle starts, and the parts will not respond to any request to access the eeprom array until the cycle finishes, approximately 4 ms. when the write protect (wp) input is a logic 0 it allows writes to both eeprom arrays. when a logic 1, it prevents any writes to the eeprom arrays. sw00640 s100111a00 a a slave address r/w acknowledge from slave acknowledge from slave command byte eeprom address 1 acknowledge from slave data for 6biteeprom 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 a x x d5 d4 d3 d2 d1 d0 a p acknowledge from slave programming begins after stop figure 12. i 2 c write of 6-bit eeprom sw00641 s100111a00 a a slave address r/w acknowledge from slave acknowledge from slave command byte eeprom address 1 acknowledge from slave slave address 00000110 1111111a 1a acknowledge from slave data from 6biteeprom 0 0 d5 d4 d3 d2 d1 d0 na p no acknowledge from master s100111a0 r/w figure 13. i 2 c read of 6-bit eeprom
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 10 s 100111a0 0 a 00000001 a a r/w acknowledge from slave acknowledge from slave acknowledge from slave data n+m p a acknowledge from slave eeprom address data n a acknowledge from slave auto-increment word address auto-increment word address data n+1 a acknowledge from slave auto-increment word address sw00642 slave address command code figure 14. i 2 c page write operation to 256 byte eeprom; m bytes where m 15 s 100111a0 0 a 00000011 a a r/w acknowledge from slave acknowledge from slave acknowledge from slave data n+m p na no acknowledge from master eeprom address auto-increment word address data n a acknowledge from master auto-increment word address s 100111a0 1a r/w acknowledge from slave sw00643 slave address command code slave address figure 15. i 2 c read operation from 256 byte eeprom; m bytes where m 1 sw00644 s100111a00 a a slave address r/w acknowledge from slave acknowledge from slave command byte eeprom address a7 acknowledge from slave slave address 000xxxxx a6a5a4a3a2a1a0a 1a acknowledge from slave data from 256eeprom d7 d6 d5 d4 d3 d2 d1 d0 na p no acknowledge from master s100111a0 r/w data latched into gpio register see figure 2 for the needed command code. figure 16. read from 256 byte eeprom and write to gpio registers
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 11 sw00645 s100111a00 aa slave address r/w acknowledge from slave acknowledge from slave command byte eeprom address acknowledge from slave a a7 a6 a5 a4 a3 a2 a1 a0 p xxxxxxxxa dummy byte acknowledge from slave gpio input port data latched 00010010 programming begins after stop see figure 2 for the needed command code. figure 17. read from gpio input port register and write to 256 byte eeprom reset power-on reset (por) when power is applied to v dd , an internal power-on reset holds the pca9558 in a reset state until v dd has reached v por . at that point, the reset condition is released and the pca9558 volatile registers and smbus state machine will initialize to their default states. the gpio outputs will be selected as inputs and in high impedance. the dip switch mux_out and non_muxed_out pin values depend on: - the mux_out_low and mux_select logic levels - the previously stored values in the eeprom register/current mux_in pin values as shown in table 2. external reset a reset of the gpio registers can be accomplished by holding the i/o_out_low pin low for a minimum of tw. these gpio registers return to their default states until the i/o_out_low input is once again high. using the pca9558 on the smbus it is possible to use intel ? chipsets to communicate with the pca9558. there are no limitations when the smbus controller is communicating with the mux or the gpio; however, there are limitations with the 2k serial eeprom. because of being able to address any location in the eeprom block using the 2nd command byte, the designer using the pca9558 on the smbus will have to program around it, an easy thing to do. the device designers had to deal with the specifics of addressing the eeprom and chose the i 2 c spec and use the 2nd command byte to address any location in the eeprom block. in order to write to the eeprom, write the eeprom address byte in the data0 byte and the data to be sent should be placed in the data1 byte. the intel ? chipset ? s word data instruction would then send the address, followed by the command register then data0 (eeprom address), and then the data1 (data byte). a read from the eeprom would be a two step process. the first step would be to do a write byte with the eeprom address in the data0 register. the second step would be to do a receive byte where the data is stored in the command register. other differences from the smbus spec: paragraph 5.5.5 - read byte/word in figure 5-11 - the pca9558 follows this same command code with one exception, the pca9558 requires 2 bytes of command before the repeated start. paragraph 5.5.6 - process call in figure 5-15 - the pca9558 read operation is very similar to the smbus process call. in the pca9558 read operation you send a start condition - slave address with a write bit - 2 bytes of command code - repeated start - slave address with a read bit - then read data . ? intel is a registered trademark of intel corporation.
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 12 typical application applications ? board version tracking and configuration ? board health monitoring and status reporting ? multi-card systems in telecom, networking and base station infrastructure equipment ? field recall and troubleshooting functions for installed boards ? general-purpose integrated i/o with dip switch and memory a central processor/controller typically located on the system main board can use the 400 khz i 2 c/smbus to poll the pca9558 devices located on the system cards for status or version control type of information. the pca9558 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the i 2 c/smbus as an intra-system communication bus. muxed eeprom control eeprom gpio i 2 c i 2 c i 2 c i 2 c asic backplane pca9544 cpu or c i 2 c philips i 2 c 4 channel multiplexer configuration settings dip switch or jumper replacement monitoring and control inputs alarm leds pca9558 card id, subroutines, configuration data, or revision history sw01080 figure 18. typical application
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 13 absolute maximum ratings 1, 2 in accordance with the absolute maximum rating system (iec 134) voltages are referenced to gnd (ground = 0 v) symbol parameter conditions rating unit v dd dc supply voltage 2.5 to 4.6 v v i dc input voltage note 3 -0.5 to v cc +0.5 v v out dc output voltage note 3 -0.5 to v cc +0.5 v t stg storage temperature range -60 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. recommended operating conditions limits symbol parameter conditions min max unit v dd dc supply voltage 3 3.6 v v il low-level input voltage scl, sda i ol = 3 ma -0.5 0.9 v v ih high-level input voltage scl, sda i ol = 3 ma 2.7 4.0 v i ol = 3 ma ? 0.4 v v ol low-level output voltage scl, sda i ol = 6 ma ? 0.6 v v il low-level input voltage mux_out_low , mux_in, mux_select -0.5 0.8 v v ih high-level input voltage mux_out_low , mux_in, mux_select 2.0 4.0 v i ol low-level output current mux_out, non_muxed_out v ol = 0.4 v ? 4 ma i oh high-level output current mux_out, non_muxed_out ? 100 a dt/dv input transition rise or fall time 0 10 ns/v t amb operating temperature 0 +70 c
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 14 dc characteristics limits symbol parameter test condition min. typ. max. unit supply v dd supply voltage 3.0 ? 3.6 v i ccl supply current operating mode all inputs = 0 v ? ? 10 ma i cch supply current operating mode all inputs = v dd ? ? 10 ma v por power-on reset voltage no load; v i = v dd or gnd ? 2.3 2.6 v input scl: input/output sda v il low-level input voltage -0.5 ? 0.8 v v ih high-level input voltage 2 ? v cc + 0.5 v i ol low-level output current v ol = 0.4 v 3 ? ? ma i ol low-level output current v ol = 0.6 v 6 ? ? ma i ih leakage current high v i = v dd -1 ? 1 a i il leakage current low v i = gnd -1 ? 1 a c i input capacitance ? ? 10 pf mux_out_low , wp, mux_select i ih leakage current high v i = v dd ? ? 1 a i il leakage current low v i = gnd ? ? -100 a c i input capacitance ? ? 10 pf mux_in a mux_in e i ih leakage current high v i = v dd ? ? 1 a i il leakage current low v i = gnd ? ? -100 a c i input capacitance ? ? 10 pf a0 inputs i ih leakage current high v i = v dd ? ? 1 a i il leakage current low v i = gnd ? ? -100 a c i input capacitance ? ? 10 pf mux_outx v ol low-level output current i ol = 100 a ? ? 0.4 v v ol low-level output current i ol = 4 ma ? ? 0.7 v i oh high-level output current v oh = v dd ? ? 100 a non_muxed out v ol low level output current i ol = 100 a ? ? 0.4 v v ol low-level output current i ol = 4 ma ? ? 0.7 v i oh high-level output current v oh = v dd ? ? 100 a gpio v ol low-level output current i ol = 100 a ? ? 0.4 v v ol low-level output current i ol = 4 ma ? ? 0.7 v i oh high-level output current v oh = v dd ? ? 100 a note: 1. v hys is the hysteresis of schmitt-trigger inputs non-volatile storage specifications parameter specification memory cell data retention 10 years min number of memory cell write cycles 100,000 cycles min application note an250 i 2 c dip switch provides additional information on memory cell data retention and the minimum number of write cycles.
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 15 ac characteristics limits symbol parameter min. typ. max. unit mux_inx ? mux_outx t plh low-to-high transition time ? 21 28 ns t phl high-to-low transition time ? 7 10 ns mux_select ? mux_outx t plh low-to-high transition time ? 20 28 ns t phl high-to-low transition time ? 8 12 ns mux_out_low ? non_muxed_out t plh low-to-high transition time ? 20 26 ns t phl high-to-low transition time ? 8 15 ns mux_out_low ? mux_outx t plh low-to-high transition time ? 20 28 ns t phl high-to-low transition time ? 7.0 15 ns t r output rise time 1.0 ? 10 ns/v t f output fall time 1.0 ? 5 ns/v c l test load capacitance on outputs ? ? ? pf i 2 c-bus t scl scl clock frequency 10 ? 400 khz t buf bus free time between a stop and a start condition 1.3 ? ? s t hd:sta hold time (repeated) start condition. after this period, the first clock pulse is generated 600 ? ? ns t low low period of scl clock 1.3 ? ? s t high high period of scl clock 600 ? -12 ns t su:sta set-up time for a repeated start condition 600 ? -32 ns t hd:dat data hold time 0 ? 10 ns t su:dat data set-up time 100 ? -100 ns t sp data spike time 0 ? 50 ns t su:sto set-up time for stop condition 600 ? 10 ns t r rise time for both sda and scl signals (10 - 400 pf bus) 20 ? 300 ns t i fall time for both sda and scl signals (10 - 400 pf bus) 20 ? 300 ns c l capacitive load for each bus line ? ? 400 pf t w write cycle time 1 ? 15 ? ms note: 1. write cycle time can only be measured indirectly during the write cycle. during this time, the device will not acknowledge it s i 2 c address.
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 16 t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl su00645 figure 19. definition of timing mux input v m v m v m mux output v ol t phl t plz v ol + 0.3v sw00766 v cc figure 20. open drain output enable and disable times definitions r l = load resistor; 1 k ? c l = load capacitance includes jig and probe capacitance; 10 pf r t = termination resistance should be equal to z out of pulse generators. pulse generator v in d.u.t. v out c l v cc r l test circuit for open drain outputs r t sw00767 v cc figure 21. test circuit
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 17 tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 18 revision history rev date description _3 20030627 product data (9397 750 11674); ecn 853-2235 29936 dated 19 may 2003. supersedes data of 2002 may 24 (9397 750 09889). modifications: ? update marketing information. ? increase number of write cycles from 3k to 100k. _2 20020524 product data (9397 750 09889); ecn 853-2235 28310 of 24 may 2002.
philips semiconductors product data pca9558 8-bit i 2 c and smbus i/o port with 5-bit multiplexed/1-bit latched 6-bit i 2 c eeprom dip switch and 2-kbit eeprom 2003 jun 27 19 purchase of philips i 2 c components conveys a license under the philips ? i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products ? including circuits, standard cells, and/or software ? described or contained herein in order to improve design and/or performance. when the product is in full production (status ? production ? ), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 06-03 document order number: 9397 750 11674 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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